This invention relates, in general, to semiconductor wafer processing, and more particularly to methods for forming power metal oxide semiconductor field effect transistor (MOSFET) devices.
Power MOSFET devices are well known and are used in many applications including automotive electronics, portable electronics, power supplies, and telecommunications. With an ever-increasing push towards cost competitive products, semiconductor manufacturers are seeking ways to reduce the costs of manufacturing semiconductor components, such as power MOSFET devices. Photolithographic processes add significant cost to the manufacture of semiconductor components. This is due in part to the cost of the equipment, the amount of labor required to process the components, and the number of steps required to provide a photolithographic pattern.
In a conventional power MOSFET process, up to eight photo-masking steps are required to produce a device. These eight steps include an active-area masking step where a thick field oxide region is left around the periphery of the device, a gate layer masking step, a base masking step, a first blocking mask for forming the source regions, a second blocking mask for forming base contact regions, a contact mask, a metal mask, and a final passivation mask. Some manufacturers have reduced the number of masking steps to four or five by incorporating self-aligned base and source regions and by eliminating the final passivation.
Although some progress has been made in reducing the number of photo-masking steps required to manufacture a power MOSFET device, methods and structures are still desirable that further reduce the number of photo-masking steps required. These methods and structures should maintain or improve device quality and performance compared to existing processes.